View LTC7149_9002132.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt c7149 1 7149fa for more information www.linear.com/LTC7149 typical application features description the lt c ? 7149 is a high efficiency 60v, 4a synchronous monolithic step-down regulator for inverting output applications. the regulator features a single resistor- programmable output voltage and high efficiency over a wide v out range. the inverting regulator operates from an input voltage range of 3.4v to 60v and provides an adjustable output from (?28v) to zero volts while delivering up to 4a of inductor current. the switching frequency is also set with an external resistor. a user-selectable mode input is provided to allow the user to trade off ripple noise for ef - ficiency at light loads; burst mode operation provides the highest efficiency at light loads, while forced continuous mode provides low output ripple. the mode/sync pin can also be used to synchronize the switching frequency to an external clock. internal level-shift circuits allow the i/o pins (run, mode/sync, pgood) to be referenced to board gnd. the LTC7149 operates with a peak current mode architec - ture that allows for fast transient response with inherent cycle-to-cycle current limit protection. applications n wide v in range: 3.4v to 60v n wide v out range: 0v to ?28v n single resistor v out programming n integrated 110m top n-channel/50m bottom n-channel mosfets n regulated i q : 440a, shutdown i q : 15a n board gnd referenced i/o pins (run, pgood, mode/sync) n accurate resistor programmable frequency (300khz to 3mhz) with 50% frequency syncrange n 92% efficiency with 12 v in and ?5v out n 0.8% output voltage accuracy n peak current mode operation n burst mode ? operation, forced continuous mode n programmable soft-start n overtemperature protection n available in 28-lead (4mm x 5mm) qfn and tssoppackages n industrial applications n telecom power supplies n distributed power systems all registered trademarks and trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5847554, 6580258. v in = 12v v in = 24v i out (a) 0 0.5 1 1.5 2 2.5 3 3.5 4 70 75 80 85 90 95 100 efficiency (%) ef?ciency with v out = ?5v 7149 ta01b efficiency with v out = ?5v v out ? ?5v 3.3a + LTC7149 7149 ta01 run v in gnd ith intv cc sw v outsns v out ? sv out ? boost mode/sync iset r t 22f 22f 2 2.2f 0.1f 100k 10nf 0.1f 200k 6.8h v in 24v 1k 4.7nf 100pf f sw = 500khz 150f 60v, 4a synchronous step-down regulator for inverting outputs
lt c7149 2 7149fa for more information www.linear.com/LTC7149 absolute maximum ratings v in voltage * ( note 3 ) ................................ 64v to ?0. 3v iset voltage * ............................................. v in to ?0. 3v gnd voltage * ............................................. 28v to ?0. 3v run voltage * ..................................... 64v to gnd ?0. 3v mode / sync , pgood voltage * .. gnd + 6v to gnd ?0. 3v v outsns voltage *....................................... v in to ?0. 3v ( note 1) order information lead free finish tape and reel part marking* package description temperature range LTC7149eufd#pbf LTC7149eufd#trpbf 7149 28-lead (4mm 5mm) plastic qfn ?40c to 125c LTC7149iufd#pbf LTC7149iufd#trpbf 7149 28-lead (4mm 5mm) plastic qfn ?40c to 125c LTC7149efe#pbf LTC7149efe#trpbf LTC7149 28-lead plastic tssop ?40c to 125c LTC7149ife#pbf LTC7149ife#trpbf LTC7149 28-lead plastic tssop ?40c to 125c consult adi marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel//. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. pin configuration 9 10 top view 29 sv out ? ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 v out ? v out ? v in v in run gnd mode/sync pgood sw sw sw sw boost intv cc extv cc ith v out ? v out ? v out ? sw sw sw pgdfb sv out ? v inreg r t v outsns iset 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, ja = 43c/w, jc = 3.4c/w exposed pad (pin 29) is sv out ? , must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v out ? v out ? v out ? v out ? v out ? v in v in run gnd mode/sync pgood pgdfb sv out ? v inreg sw sw sw sw sw sw sw boost intv cc extv cc ith iset v outsns r t 29 sv out ? t jmax = 125c, ja = 30c/w, jc = 5c to 10c/w exposed pad (pin 29) is sv out ? , must be soldered to pcb r t , pgdfb , ith , v inreg ..... intv cc +0. 3v to ( sv out ? ?0. 3v ) extv cc voltage * ....................................... 28v to ?0. 3v operating junction temperature range ( notes 4 , 6) ........ ? 40 c to 125c storage temperature range .................. ? 65 c to 125c * all voltage referenced to v out ? , unless otherwise specified . http://www .linear.com/product/LTC7149#orderinfo
lt c7149 3 7149fa for more information www.linear.com/LTC7149 electrical characteristics symbol parameter conditions min typ max units v in input supply operating voltage range 3.4 60 ? |v out ? | v v out ? output operating voltage range (note 3) ?28v ?0.05 v i vin input quiescent current shutdown mode; v run = 0v burst mode operation fc mode (note 5) 18 440 1.4 30 600 2.5 a a ma i iset reference current v iset + |v out ? | = 3.3v l 49.6 49.4 50 50 50.4 50.6 a a ?v out(load+line) output voltage load + line regulation l 0.1 0.5 % v ea(offset) error amp input offset v iset = 3.3v ?5 5 mv g m (ea) error amplifier transconductance v ith + |v out ? | = 0.7v, v out ? = ?3.3v 400 550 700 s i lsw topside nmos switch leakage 0.1 1 a r sw resistance to v out ? 0.5 1 1.5 m r ds(on) topside nmos on-resistance bottom side nmos on-resistance 110 50 m m t on(min) minimum on-time 60 ns v run run input rising run hysteresis l 1.08 1.2 120 1.32 v mv i run run input current v run = 12v 0 10 na v mode/sync burst mode operation fc mode v mode/sync = 0v 1.2 0.4 v v i mode/sync mode/sync input current v mode/sync = 0v ?8 ?5 a i lim peak current limit l 5.7 5.4 6 6 6.3 6.6 a a v uvlo v intvcc + |v out ? | undervoltage lockout v in rising l 2.4 2.65 2.9 v v uvlo(hys) v intvcc + |v out ? | undervoltage lockout hysteresis 200 mv v ovlo v in overvoltage lockout rising (v in + |v out ? |) 64 68 v v ovlo(hys) v in overvoltage lockout hysteresis 2 4 v f osc oscillator frequency rt = 100k l 0.92 1 1.08 mhz f sync sync capture range % of programmed frequency 50 150 % v intvcc v intvcc ldo output voltage (v intvcc + |v out ? |) v in > 3.6v, v extvcc + |v out ? | = 0v v in > 5.0v, v extvcc + |v out ? | > 3.2v 3.25 2.85 3.45 3 3.65 3.15 v v v extvcc extv cc switchover voltage v extvcc + |v out ? | l 3.1 3.25 3.15 3.2 v v r voutsns v outsns resistance to sv out ? 80 100 120 k i pgdfb pgdfb leakage current v pgdfb = 0.6v 0 100 na ov pgdfb output overvoltage pgood upper threshold v pgfb + |v out ? | rising 0.63 0.645 0.66 v uv pgdfb output undervoltage pgood lower threshold v pgfb + |v out ? | falling 0.54 0.555 0.57 v ?v pgdfb pgood hysteresis 10 mv r pgood pgood pull-down resistance 550 i pgood(leak) pgood leakage current v pgood = 3.3v 100 na the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v in = 24v, v extvcc = 0v unless otherwise specified.
lt c7149 4 7149fa for more information www.linear.com/LTC7149 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: transient absolute maximum voltages should not be applied for more than 4% of the switching duty cycle. note 3: minimum on-time considerations need to be taken into account when regulating to an output voltage close to zero. refer to minimum on- time section in operations for more details. note 4: the LTC7149 is tested under pulsed load conditions such that t j t a . the LTC7149e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the ?40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC7149i is guaranteed over the full ?40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 5: the quiescent current in fc mode does not include switching loss of the power fets. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. symbol parameter conditions min typ max units t pgood pgood delay pgood low to high pgood high to low 16 64 switch cycles switch cycles v vinreg input voltage regulation voltage (v inreg + |v out ? |) l 1.85 2 2.15 v i vinreg v inreg leakage current 0 100 na
lt c7149 5 7149fa for more information www.linear.com/LTC7149 typical performance characteristics iset voltage line regulation quiescent current vs temperature shutdown current vs v in load regulation iset current vs temperature iset current vs v iset i out (a) 0 normalized v out (%) 99 4 7149 g01 98 2 1 3 101 100 fc mode burst mode operation v in = 24v v out = ?5v temperature (c) ?55 i set (a) 49.7 125 7149 g02 49.5 ?15?35 5 4525 65 10585 50.5 49.9 50.1 50.3 v iset 0 i set (a) 47 24 7149 g03 46 4 8 1612 20 51 48 49 50 v in = 24v v in (v) 0 v iset (v) 4.96 60 7149 g04 4.95 10 20 4030 50 5.01 4.97 4.99 5.00 r iset = 100k temperature (c) ?55 i q (a) 100 125 7149 g05 0 ?15?35 5 4525 65 10585 500 200 300 400 shutdown sleep v in (v) 0 i q (a) 4 60 7149 g06 0 10 20 4030 50 20 8 12 16 r ds(on) vs temperature transient response, ccm transient response, dcm temperature (c) ?55 r dson (m) 40 125 7149 g07 0 ?35 ?15 65 10585 5 4525 200 80 120 160 mtop mbot v in = 24v, v out = ?3.3v i out = 0a to 3a, l = 2.2h, f sw = 1mhz r ith = 1k, c ith = 2.2nf, c ithp = 100pf c out = 2 22f + 150f 20s/div v out ac?coupled 100mv/div i l 3a/div i load 3a/div 7149 g08 v in = 24v, v out = ?3.3v i out = 0.2a to 2a, l = 2.2h, f sw = 1mhz r ith = 1k, c ith = 2.2nf, c ithp = 100pf c out = 2 22f + 150f 20s/div v out ac?coupled 100mv/div i l 2a/div i load 2a/div 7149 g09
lt c7149 6 7149fa for more information www.linear.com/LTC7149 typical performance characteristics switching frequency/period vs r t switching frequency vs temperature start-up waveform discontinuous conduction mode operation continuous conduction mode operation run rising threshold vs temperature rt resistor (k) 0 frequency (mhz) period (ns) 0.5 350 7149 g10 0 150 200 50 100 300250 3.0 1.0 1.5 2.0 2.5 1000 500 0 3500 1500 2000 2500 3000 frequency period temperature (c) ?55 frequency (khz) 990 125 7149 g11 985 ?15?35 5 4525 65 10585 1010 995 1000 1005 temperature (c) ?55 run rising threshold (v) 1.185 125 7149 g15 1.180 ?15?35 5 4525 65 10585 1.210 1.190 1.195 1.200 1.205 efficiency vs load current, v out ? =? 5v efficiency vs load current, v out ? =? 12v maximum output current vs input voltage 5ms/div v run 2v/div v out ? 5v/div v pgood 5v/div i l 2a/div 7149 g12 2s/div v sw 10v/div i l 1a/div 7149 g13 500ns/div v sw 10v/div i l 1a/div 7149 g14 v out = ?3.3v v out = ?5v v out = ?12v v in (v) 0 10 20 30 40 50 60 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 i out (a) maximum load current vs. v in 7149 g16 v in = 12v v in = 24v v in = 36v v in = 48v i out (a) 0 0.5 1 1.5 2 2.5 3 3.5 4 70 75 80 85 90 95 100 efficiency (%) ?5v out 7149 g17 v in = 12v v in = 24v v in = 36v v in = 48v i out (a) 0 0.5 1 1.5 2 2.5 3 3.5 4 60 65 70 75 80 85 90 95 100 efficiency (%) out 7149 g18
lt c7149 7 7149fa for more information www.linear.com/LTC7149 pin functions v out ? ( pins 1, 2 , 26-28/pins 1-5): negative output of the step-down regulator. v in ( pin 3, 4/pins 6, 7): input supply pin of the step- down regulator. run ( pin 5/pin 8): logic controlled run input. do not leave this pin floating. place a resistor divider from v in to gnd for an accurate v in undervoltage threshold. gnd ( pins 6/pins 9): board ground sense pins. connect pins to pcb ground. mode/sync ( pin 7/pin 10): mode select and oscillator synchronization input of the step-down regulator. leave mode/ sync floating for forced continuous mode opera - tion or tie mode/sync to gnd for burst mode operation. furthermore, connecting mode/ sync to an external clock will synchronize the internal oscillator to the external clock signal and put the part in forced continuous mode. pgood ( pin 8/pin 11): v out ? within regulation indica - tor. pgood is pulled to gnd when v pgdfb is more than 0.645v or less than 0.555v with respect to v out ? . pgdfb ( pin 9/pin 12): power good feedback. place a resistor divider from gnd to v out ? to detect power good level. vinreg ( pin 11/pin 14): input voltage regulation sense input . place a resistor divider from v in to v out ? to program the level of input voltage regulation. to disable feature, connect the pin to intvcc. r t ( pin 12/pin 15): oscillator frequency programming pin. connect an external resistor between 500k to 40k from r t to sv out ? to program the frequency from 200khz to 2.5mhz respectively. since the synchronization range is limited to 50% of the set frequency, be sure that either the external clock is within this range or r t is set to ac- commodate the external clock for proper frequency lock. v outsns ( pin 13/pin 16): output voltage error amplifier input pin. for majority of applications, connect this pin to gnd. iset ( pin 14/pin 17): accurate 50a bias current and positive input to the error amplifier . connect an external resistor from this pin to v out ? to program the output voltage. connecting an external capacitor from iset to v out ? will soft start the output voltage by reducing current inrush during start-up. ith ( pin 15/pin 18): error amplifier output and switching regulator compensation point. the current comparator?s trip threshold is linearly proportional to this voltage. tying this pin to intv cc activates internal compensation. extv cc ( pin 16/ pin 19): external power input to the internal regulator. the internal regulator will draw cur - rent from extv cc instead of v in when extv cc is tied to a voltage higher than 3.2v above v out ? and v in is 5v above v out ? . for output voltages at or below ?3.3v, this pin can be tied to gnd. if this pin is tied to a supply other than gnd, locally bypass with at least a 1f to v out ? . intv cc ( pin 17/pin 20): low dropout regulator. locally bypass with at least 1f to v out ? . boost ( pin 18/pin 21): boosted floating driver supply for internal top power mosfet . place a 0.1f bootstrap capacitor between boost and sw. sw (pins 19-25/pins 22-28): switch node connection to the inductor of the regulator. sv out ? ( pins 10, 29/pins 13, 29): the exposed pad must be soldered to a pcb metal plane to sv out ? for electrical connection and rated thermal performance. (qfn/tssop)
lt c7149 8 7149fa for more information www.linear.com/LTC7149 functional diagram + ? + ? + ? ? + 0a sv out ? v out ? gnd ? + intv cc extv cc r t mode/sync boost buck logic and gatedrive v in sw pgdfb pgood vinreg run 2v iset v outsns ith level shift osc pgood logic 1/50k ldo clk peak-current comparator reverse comparator intv cc 50a 7149 bd v in sv out ? sv out ? 100k sv out ? sv out ?
lt c7149 9 7149fa for more information www.linear.com/LTC7149 operation the LTC7149 is a current mode monolithic step-down regulator. the accurate 50 a bias current on the iset pin allows the user to program the output voltage in a unity-gain buffer fashion with just one external resistor, r set , from the iset pin to v out ? . the output voltage is set such that: v out ? = ?50a ? r set the LTC7149 operates through a wide v in range, and its frequency can be programmed to a wide range with the r t resistor. to suit a variety of applications, the mode/sync pin allows the user to trade off output ripple for efficiency. main control loop in normal operation, the internal top power mosfet is turned on at the beginning of a clock pulse. the inductor current is allowed to ramp up to a peak level . once that level is reached , the top power switch is turned off and the bottom switch is turned on until the next clock cycle. the peak inductor current is determined by sensing the voltage drop across the sw and v in nodes of the top power mosfet. the voltage on the ith pin sets the comparator threshold corresponding to inductor peak current. the error amplifier, ea, adjusts this ith voltage by comparing the differential v outsns voltage to v out ? with the voltage on iset . in the typical application where the v outsns pin is tied to gnd, if the load current into v out ? increases, it causes an increase in v iset with respect to v outsns . this causes the ith voltage to rise until the current into v out ? provided by the regulator matches that of the load current. low current operation burst mode operation can be selected by connecting the mode/sync pin to gnd. in this mode, the LTC7149 will automatically transition from continuous mode operation to burst mode operation when the load current is low. a reverse current comparator looks at the voltage across sw to gnd and turns off the bottom power mosfet when that voltage difference approaches zero. this prevents the inductor current from going negative. an internal burst clamp is set to be approximately 1a, which means that in burst mode, the peak inductor current will never go below 1a regardless of what the ith voltage demands the peak current to be. as a result, when the load is low enough, v outsns will rise relative to v iset because the average programmed inductor current is above the load current, thus driving v ith low. once the ith voltage is driven below an internal threshold (~400mv), the switching regulator will enter its sleep mode and wait for v out to drop and v ith to rise above the threshold before it starts to switch again. during sleep mode, the quiescent current of the part is reduced to 440a to conserve input power. the LTC7149 is designed to operate with single burst pulse behavior to minimize output voltage ripple while keeping the efficiency high at light loads . lastly, if at any point the top power mosfet is on for roughly 8 consecutive cycles, the part will turn on the bottom power mosfet for a brief duration such that the boost capacitor can be replenished. forced continuous mode operation floating the mode/sync pin defaults the LTC7149 into forced continuous mode operation . in this mode, the part switches continuously regardless of load current, and the inductor peak current is allowed to decrease to approxi - mately ? 1a to allow for significant negative average current. high duty cycle/dropout operation as the input voltage decreases towards the desired output voltage, the duty cycle will increase towards 100%. how - ever, given the architecture, there are two restrictions that prevent the LTC7149 from operating in full dropout mode. the first restriction is due to how the iset voltage is programmed. if a resistor is placed between iset and v out ? to set the output voltage, the 50a of current out of the iset pin is only guaranteed to be accurate when v iset is more than 500mv below v in . as the input volt - age drops below that 500mv threshold, the iset current will decrease, thus limiting the programmed voltage. typically, v iset will never get within 300mv of v in . since v iset programs v out ? , this limitation essentially enforces a maximum duty cycle for the switcher. this limitation can be overcome if an accurate external supply is used to drive the iset pin directly.
lt c7149 10 7149fa for more information www.linear.com/LTC7149 operation the second limitation against full dropout operation is the requirement for the boost to sw capacitor to refresh. when the top power mosfet is on indefinitely during dropout operation, the boost to sw capacitor slowly gets depleted by the internal circuitry of the chip . when the bottom switch does not turn on for at least 80ns for 8 periods, it is forced to turn on in order to guarantee sufficient voltage on the bootstrap capacitor. during a refresh, the bottom switch will only turn on for roughly 30% of the period to limit inductor ripple, thus limiting output voltage ripple. input voltage regulation in certain applications, the input supply to the power regu - lator can exhibit fairly high output impedance. as a result, when the regulator is running at heavy loads, v in might droop more than desired . the input voltage regulation loop allows the application to be programmed to decrease the peak inductor current level, and consequently the input current draw, when it senses that the input voltage has dropped below a programmed threshold. if v inreg ever falls below 2v above v out ? , the regulator will decrease the output current level in order to maintain the 2v at the pin. if this feature is not required, tie the v inreg pin to intv cc to prevent this control loop from interfering with normal operation. intv cc regulator the LTC7149 has two onboard internal low dropout (ldo) regulators that power the drivers and internal bias circuitry. regardless of which one is in operation , the intv cc must be bypassed to v out ? with a minimum of 2.2f ceramic capacitor. good bypassing is necessary to supply the high transient current required by the power mosfet gate drivers. the first ldo is powered from v in , and the intv cc voltage is regulated to 3. 3v above v out ? . the power dissipated across this ldo would thus be equal to (v in + |v out ? |?3.3v)? i intvcc . for a typical 1mhz application running in ccm, the current drawn from intv cc by the chip is roughly 20ma. thus, if the input voltage is high, the power loss and heat rise due to this ldo might be quite significant. to combat this issue , a separate ldo exists that is powered from extv cc . as long as the input voltage is above 5v and the extv cc voltage is >3. 2v above v out ? , this ldo will take over and regulate the intv cc voltage to 3.1v above v out ? . in applications where the output voltage is programmed to ?3.3v or below, it is recommended that the extv cc pin be directly tied to the gnd pin. furthermore, if a separate lower voltage rail exists on board that can supply intv cc current, then attaching that supply to extv cc will also suffice provided that a 1f ceramic bypass capacitor is placed from the extv cc pin to v out ? physically close to the chip. both examples should significantly reduce the power loss through the ldo. v in undervoltage programming LTC7149 offers an accurate run threshold to start the regulator. as a result, a resistor divider from v in to gnd can be placed with the intermediate node fed back to run to set an accurate v in undervoltage threshold . as the input voltage rises, the run voltage will increase above the v run rising threshold (1.2v), and the regulator will turn on. similarly, once on, if the input voltage decreases below the v run falling threshold (1.1v), the regulator will turn off. v in overvoltage protection in order to protect the internal power mosfet devices against transient voltage spikes, the LTC7149 constantly monitors the v in pin for an overvoltage condition. when v in + |v out ? | rises above v ovlo the regulator suspends operation by shutting off both power mosfets and dis - charges the iset pin voltage to ground. once v in drops below v ovlo ? v ovlo(hyst) , the regulator resumes normal switching operation. programming switching frequency connecting a resistor from the r t pin to sv out ? programs the switching frequency from 200khz to 3mhz according to the following formula: frequency (hz) = 10 11 1 / f ( ) r t ( ? ) do not float the r t pin.
lt c7149 11 7149fa for more information www.linear.com/LTC7149 operation the internal phase-locked loop has a synchronization range of 50% around its programmed frequency. therefore, during external clock synchronization, the proper r t value should be selected such that the external clock frequency is within this 50% range of the r t programmed frequency. output voltage tracking and soft-start the LTC7149 allows the user to program its output voltage ramp rate by means of the iset pin. since v outsns servos its voltage to that of v iset , placing an external capacitor c set from the iset pin to v out ? will program the ramp-up rate of the iset pin and thus the v out ? voltage. v out ? (t) = i iset ? r set 1 ? e 1 r set ? c set ? ? ? ? ? ? ? ? ? ? ? ? ? ? from 0% to 90% v out ? : t ss ? ?r set ? c set ? in(1 ? 0.9) t ss ? 2.3 ? r set ? c set the soft-start time t ss ( from 0% to 90% of v out ) is 2.3 times the time constant (r set ? c set ). the iset pin can also be driven by an external supply capable of sinking 50a. when starting up into a pre-biased v out ? , the LTC7149 will stay in burst mode operation and keep the power switches off until the voltage on iset has ramped up to be equal to v outsns , at which point the switcher will begin switching and v out ? will start to decrease at the rate to maintain: v iset = v outsns . output power good when the LTC7149? s output voltage is within the 7.5% window of the regulation point, which is divided down as a v pgdfb voltage in the range of 0.555v to 0.645v with respect to v out ? , the output voltage is in regulation and the pgood pin is pulled high with an external resistor connected to a voltage rail less than 6v above gnd. oth - erwise, an internal open-drain pull-down device will pull the pgood pin low to gnd. to prevent unwanted pgood glitches during transients or dynamic v out ? changes, the LTC7149? s pgood falling edge includes a blanking delay of approximately 64 clock cycles. internal/external ith compensation for ease of use, the user can simplify the loop compen - sation by tying the ith pin to intv cc to enable internal compensation. because the internal compensation is required to provide a stable output voltage for a wide range of switching frequencies, it is designed to have a loop response that is typically much slower than optimal. this thus becomes a trade-off between simplicity and opti-loop ? optimization, where ith components are external and are selected to optimize the loop transient response with minimum output capacitance. minimum on-time considerations due to the architecture of the LTC7149, a minimum on-time restriction is imposed such that the top power mosfet can have enough time to turn on and accurately determine if it has reached its peak current level before shutting off. the typical minimum on-time of the regulator is 60ns. thus, given an application with varying input and output voltage ranges, the frequency must be designed to be slow enough to ensure the minimum on-time restriction is not violated. in the rare cases where the minimum on-time restriction is violated, the frequency of the LTC7149 will automatically and gradually fold back down to one-fifth of its programmed switching frequency to allow the output to remain in regu - lation. this feature is designed for applications where the input voltage only experiences momentary spikes in volt - age. in such applications, the frequency does not have to be programmed so slow to account for those momentary spikes, thus significantly saving component size and cost. t on(min) = | v out ? | v in(max) + | v out ? | ? 1 f sw choose the appropriate switching frequency to guarantee the t on(min) does not approach the minimum on-time number. the minimum on-time occurs at maximum v in .
lt c7149 12 7149fa for more information www.linear.com/LTC7149 input capacitor (c in ) selection the input capacitance, c in , is needed to filter the square wave current at the drain of the top power mosfet . to prevent large input voltage droops from occurring, a low effective series resistance (esr) input capacitor sized for the maximum rms current should be used. the maximum rms current is given by: i rms ? i out(max) ? | v out ? | v in this formula has a maximum at v in = |v out ? |, where i rms ? i out . this simple worst-case condition is com - monly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. output capacitor (c out ) selection the selection of c out is determined by the esr that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. when the top power fet is on, the current into the v out ? terminal of c out is equal to the load current, i load . when the bottom power fet is on, the current into the v out ? applications information terminal of c out is equal to the load current subtracted by the inductor current, i l . in equilibrium, the charge lost during one phase is replenished in the other, and the output ripple, ?v out(charge) ? , is determined by: ? v out(charge) ? i out f sw ? c out | v out ? | v in + | v out ? | ? ? ? ? ? ? ? ? ? ? the esr of the c out is also a major factor in total output voltage ripple. the ripple due to esr is: ? v out(esr) ? i lpk ? r esr , where : i lpk = i out v in + | v out ? | v in ? ? ? ? ? ? ? ? ? ? + v in ? | v out ? | 2f sw ? l ? (v in + | v out ? |) the total output voltage ripple is thus : ?v out = ?v out(charge) + ?v out (esr) multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements . dry tantalum , special polymer , aluminum electrolytic and ceramic capacitors are all available in surface mount packages . special polymer capacitors are very low esr but have lower capacitance density than other types . tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies . aluminum electrolytic capacitors have significantly higher esr , but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability . ceramic capacitors have excellent low esr characteristics and small footprints .
lt c7149 13 7149fa for more information www.linear.com/LTC7149 using ceramic input and output capacitors higher value, lower cost ceramic capacitors are now be- coming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when only a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, use x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high fre - quency bypassing, since the impedance to the supply is very low . a 22f ceramic capacitor is usually enough for these conditions. place this input capacitor as physically close to the v in pin as possible. inductor selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ?i l = ?v in(max) f sw ? l | | v out ? | v in(max) + | v out ? | ? ? ? ? ? ? ? ? ? ? ? ? lower ripple current reduces core losses in the inductor and reduces output voltage ripple. however, at extremes, low ripple causes inductor current sensing issues. high - est efficiency operation is obtained at low frequency with reasonably small ripple current. however, achieving this requires a large inductor. there is a trade-off between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 2a. to guarantee that ripple current does not exceed specified inductor saturation current ratings, the inductance should be chosen according to: l = v in(max) f sw ? ?i l(max) | v out ? | v in(max) + | v out ? | ? ? ? ? ? ? ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. core loss is very dependent on the material, frequency and inductance selected . higher inductance reduces ripple. unfortunately, increased inductance re - quires more turns of wire and therefore copper losses will increase. ferrite materials have very low core losses and are pre - ferred at high switching frequencies, so design goals can minimize copper loss and preventing saturation . however , ferrite core material saturates ?hard?, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/ current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don? t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. new designs for surface mount inductors are available from toko , vishay, nec/tokin, cooper, tdk and wurth elektronik. refer to table 1 for more details. applications information
lt c7149 14 7149fa for more information www.linear.com/LTC7149 applications information table 1. inductor selection table inductor inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) manufacturer xal8080 series 4.7 8.89 17.4 8.6 8.1 8.0 coilcraft www.coilcraft.com 6.8 13.20 14.0 8.6 8.1 8.0 10.0 21.00 10.9 8.6 8.1 8.0 xal1010 series 3.3 3.70 27.4 11.3 10 10.0 4.7 5.20 25.4 11.3 10 10.0 5.6 6.30 23.6 11.3 10 10.0 6.8 8.10 21.8 11.3 10 10.0 8.2 11.70 18.3 11.3 10 10.0 10.0 13.40 17.5 11.3 10 10.0 15.0 16.9 15.5 11.3 10 10.0 fdv0840 series 2.1 10.40 10.6 9.1 8.4 4.0 toko www.toko.com 3.9 18.80 8.4 9.1 8.4 4.0 4.9 24.60 6.9 9.1 8.4 4.0 6.9 31.70 6.1 9.1 8.4 4.0 ihlp-4040dz-a1 series 2.2 8.20 25.6 11.5 10.3 4.0 vishay www.vishay.com 3.3 13.70 18.6 11.5 10.3 4.0 4.7 15.00 17.0 11.5 10.3 4.0 5.6 17.60 16.0 11.5 10.3 4.0 6.8 21.20 13.5 11.5 10.3 4 .0 10.0 33.20 12.0 11.5 10.3 4.0 we-hci 1050 series 2.4 3.50 17.0 10.6 10.6 5.0 wurth elektronik www.we-online.com 3.3 5.90 15.0 10.6 10.6 5.0 4.2 7.10 14.0 10.6 10.6 5.0 5.5 10.30 12.0 10.6 10.6 5.0 6.5 12.50 10.0 10.6 10.6 5.0 7.8 13.60 9.5 10.6 10.6 5.0 10.0 16.30 8.5 10.6 10.6 5.0
lt c7149 15 7149fa for more information www.linear.com/LTC7149 checking transient response the opti-loop external compensation allows the tran - sient response to be optimized for a wide range of loads and output capacitors via the ith pin. this allows for optimization of the control loop behavior and provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects these closed-loop responses. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. the typical application section provides adequate starting points for different applications . the rc filter sets the dominant pole-zero loop compensation. the values can be modified slightly ( from 0. 5 to 2 times their suggested value) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out ? immedi- ately shifts by an amount equal to the ?i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out ? to its steady-state value. during this recovery time, v out ? can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the band - width of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. the gain of the loop increases with the r ith and the bandwidth of the loop increases with decreasing c ith . if r ith is increased by the same factor that c ith is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in most critical frequency ranges of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance . for a detailed explanation of optimizing the compensation components, including a review of control loop theory , refer to analog devices application note 76. max output current the maximum output current for the LTC7149 is equal to: i out(max) = 4a ? (1? d eff ) such that d eff denotes the effective duty cycle of the application. on the first order, d eff | v out ? | v in + | v out ? | however, voltage drops across the power switches and inductor dcr leads to errors in that approximation. d eff = | v out ? | + 4a ? r l + 4a ? r bot v in + | v out ? | ? 4a ? r top + 4a ? r bot d eff = | v out ? | + 4a ? r l + 0.2v v in + | v out ? | ? 0.24v where r l is the dcr of the inductor. refer to maximum output current vs input voltage in the typical performance characteristics section for a quick reference. output short considerations in an event where the output of the LTC7149 is shorted to gnd through a low resistance , high inductance trace/ wire, it is likely for the v out ? voltage to momentarily spike applications information
lt c7149 16 7149fa for more information www.linear.com/LTC7149 above board gnd. in a typical application where the gnd and v outsns pins are tied directly to the board gnd, it would violate the absmax specification of those pins and potentially cause damage to the ic. to prevent damage in this case, connect a 100 resistor between the v outsns pin to board gnd, and a 20 resistor between the gnd pin to board gnd. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual power losses to de - termine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% ? (p1 + p2 + p3 +?) where p1, p2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses , three main sources usually account for most of the losses in LTC7149 circuits: 1) i 2 r losses, 2) switching and biasing losses, 3) other losses. 1. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current flows through inductor l but is ? chopped? between the internal top and bottom power mosfets . thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (d) as follows: r sw = (r ds(on)top )(d) + (r ds(on)bot )(1 ? d) applications information the r ds( on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 2. the switching current is the sum of the mosfet driver and control currents. the power mosfet driver cur - rent results from switching the gate capacitance of the power mosfets . each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/ dt is a current out of v in that is typically much larger than the dc control bias current. in continuous mode: i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom power mosfets and f is the switching frequency. the power loss is thus: switching loss = i gatechg ? v in the gate charge loss is a function of current through the intv cc pin as well as frequency. thus, their effects will be more pronounced in application with high ldo supply voltages ( either extv cc or v in ) and higher frequencies. 3. other ?hidden? losses such as transition loss and cop - per trace and internal load resistances can account for additional efficiency degradations in the overall power system. it is very important to include these ?system? level losses in the design of a system . transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions . the LTC7149 internal power devices switch quickly enough that these losses are not signifi - cant compared to other sources . other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss.
lt c7149 17 7149fa for more information www.linear.com/LTC7149 thermal conditions in a majority of applications, the LTC7149 does not dis - sipate much heat due to its high efficiency and low thermal resistance of its exposed-back qfn and fe packages . how - ever, in applications where the LTC7149 is running at high ambient temperature, high v in , high switching frequency, and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 180c, both power switches will be turned off until the temperature drops by 15c. to avoid the LTC7149 from exceeding the maximum junc - tion temperature, some thermal analysis must be done. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja as an example, consider the case when the LTC7149 is used in applications where v in = 24v, v out ? = ?5v, i out = 4a1 and f = 1mhz. the equivalent power mosfet resistance r sw is: r sw = r ds(on)top ? | v out ? | v in + | v out ? | + r ds(on)bot ? 1? | v out ? | v in + | v out ? | ? ? ? ? ? ? ? ? ? ? = 110m ? ? 5v 29v + 50m ? ? 1? 5v 29v ? ? ? ? ? ? ? ? = 60.3m ? in the case where the extv cc pin is connected to the gnd, the v in current will be minimal as most of the current used to bias up internal circuitry and gate drive will come directly from extv cc . typically for a 1mhz application, the current drawn from extv cc will be 20ma. therefore, the total power dissipated by the part is: p d = i out 2 ? r sw + v extvcc ? i extvcc = 16a 2 ? 60.3m ?+ 5v ? 20ma = 1.07w the fe28 package junction-to-ambient thermal resistance, ja , is around 30 c/w. therefore, the junction temperature of the regulator operating in a 25c ambient temperature is approximately: t j = 1.07w ? 30c/w + 25c = 57c remembering that the above junction temperature is obtained from an r ds(on) at 25c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. redoing the calculation assuming that r sw increased 10 % at 57c yields a new junction temperature of 63c. if the application calls for a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or air flow. board layout considerations when laying out the printed circuit board , the following checklist should be used to ensure proper operation of the LTC7149 ( refer to figure 1). check the following in your layout: 1. do the capacitors c in connect to the v in and v out ? as close as possible? these capacitors provide the ac cur - rent to the internal power mosfets and their drivers. 2. are c out and l closely connected? the (+) plate of c out returns current to gnd and the (?) plate of c in . 3. solder the exposed pad (pin 29) on the bottom of the package to the sv out ? plane. connect this sv out ? plane to other layers with thermal vias to help dissipate heat from the LTC7149. 4. the ground terminal of the iset resistor must be con - nected to the other quiet signal sv out ? and together connected to the power v out ? on only one point. the iset resistor should be placed and routed away from noisy components and traces, such as the sw line, and its trace should be minimized. applications information
lt c7149 18 7149fa for more information www.linear.com/LTC7149 5. keep sensitive components away from the sw pin . the iset resistor , r t resistor , the compensation compo- nents c ith and r ith , and the intv cc bypass caps should be routed away from the sw trace and the inductor. 6. a ground plane is preferred. 7. flood all unused areas on all layers with copper, which reduces the temperature rise of power components. these copper areas should be connected to gnd. design example as a design example, consider the LTC7149 in an applica - tion with the following specifications: v in = 24v to 36v v out ? = ?5v i out(max) = 3a i out(min) = 500ma f sw = 1mhz first, the r set is selected based on: r set = v out 50a = 5v 50a = 100k ? = 2.3 ? r set ? c set ? c set = 8.7nf a typical 10nf capacitor can be used for c set . because efficiency is important at both high and low load current, burst mode operation will be utilized. select from the characteristic curves the correct r t resistor for the 1mhz switching frequency. based on that, r t should be 100k. then calculate the inductor value to achieve a cur - rent ripple that is about 40% of the maximum load current at maximum v in : l = 36v 1mhz ? 2.4a ? ? ? ? ? ? ? ? 5v 41v ? ? ? ? ? ? ? ? = 1.8h c out will be selected based on the esr that is required to satisfy the output ripple requirement and the bulk ca - pacitance needed for loop stability. for this design, two 47f ceramic capacitors will be used. c in should be sized for a maximum current rating of: i rms = 3a 5v 24v = 1.37a decoupling the v in pin with one 22f ceramic capacitor is adequate for most applications. applications information
lt c7149 19 7149fa for more information www.linear.com/LTC7149 typical applications 12v input to ?5v output at 1mhz operation transient response 2.4h l1 c in2 0.1f c in 22f c vcc 2.2f c out 22f 4 c boost 0.1f r set 100k c set 10nf r ith 1.4k c ithp 220pf c ith 2.2nf r t 100k 12v run LTC7149 v in gnd boost sw v outsns v out ? s v out ? v in mode/sync extv cc intv cc v inreg iset ith v out ? ?5v 2.8a r t 7149 ta03 300ma?1.8a?300ma 20s/div v out 100mv/div i l 2a/div i load 2a/div 7149 ta03b
lt c7149 20 7149fa for more information www.linear.com/LTC7149 typical applications 12v input to ?12v output at 1mhz operation 6.5h l1 c in2 0.1f c in 22f c vcc 2.2f c out 22f 4 c boost 0.1f r set 240k c set 10nf r ith 845 c ithp 220pf c ith 4.7nf r t 100k 12v run LTC7149 v in gnd boost sw v outsns v out ? s v out ? v in mode/sync intv cc v inreg iset ith v out ? ?12v 2a r t extv cc 7149 ta04 200ma?1.2a?200ma 20s/div 7149 ta04b v out 200mv/div i l 2a/div i load 1a/div transient response
lt c7149 21 7149fa for more information www.linear.com/LTC7149 typical applications 24v input to ?5v output at 1mhz operation transient response 2.4h l1 c in2 0.1f c in 22f c vcc 2.2f c out 22f x 4 c boost 0.1f r set 100k c set 10nf r ith 1.5k c ithp 150pf c ith 1.5nf r t 100k 24v run LTC7149 v in gnd boost sw v outsns v out ? sv out ? v in mode/sync intv cc v inreg iset ith v out ? ?5v 3.3a r t extv cc 7149 ta05 300ma?1.8a?300ma 20s/div 7149 ta05b v out 100mv/div i l 2a/div i load 2a/div
lt c7149 22 7149fa for more information www.linear.com/LTC7149 typical applications 24v input to ?12v output at 1mhz operation 7.8h l1 c in2 0.1f c in 22f c vcc 2.2f c out 22f 4 c boost 0.1f r set 240k c set 10nf r ith 1.33k c ithp 220pf c ith 3.3nf r t 100k 24v run LTC7149 v in gnd boost sw v outsns v out ? sv out ? v in mode/sync intv cc v inreg iset ith v out ? ?12v 2.6a r t extv cc 7149 ta06 20s/div 7149 ta06b v out 100mv/div i l 2a/div i load 1a/div transient response
lt c7149 23 7149fa for more information www.linear.com/LTC7149 typical applications 24v input to ?24v output at 1mhz operation 15h l1 c in2 0.1f c in 22f c vcc 2.2f c out 22f 4 c boost 0.1f r set 480k c set 10nf r ith 1.33k c ithp 220pf c ith 3.3nf r t 100k c out2 33f 24v run LTC7149 v in gnd boost sw v outsns v out ? sv out ? v in mode/sync intv cc v inreg iset ith v out ? ?24v 2a r t extv cc 7149 ta07 20s/div 7149 ta07b v out 50mv/div i l 1a/div i load 500ma/div transient response
lt c7149 24 7149fa for more information www.linear.com/LTC7149 package description please refer to http://www .linear.com/product/LTC7149#packaging for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wghd-3). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0816 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev c)
lt c7149 25 7149fa for more information www.linear.com/LTC7149 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. package description please refer to http://www .linear.com/product/LTC7149#packaging for the most recent package drawings. fe28 (eb) tssop rev l 0117 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev l) exposed pad variation eb revision history rev date description page number a 03/18 clarified absolute maximum ratings clarified functional diagram clarified board layout considerations 2 8 17
lt c7149 26 7149fa for more information www.linear.com/LTC7149 lt 0318 rev a ? printed in usa www.linear.com/LTC7149 ? analog devices, inc. 2016 related parts typical application 24v input concurrent 12v supply part number description comments ltc3649 60v, 4a synchronous rail-to-rail single resistor step-down regulator v in(min) = 3.1v, v in(max) = 60v, v out(min) = 0v, 4mm 5mm qfn-28, tssop-28e ltc3600 15v, 1.5a synchronous rail-to-rail single resistor step-down regulator v in(min) = 4v, v in(max) = 15v, v out(min) = 0v, msop-12, 3mm 3mm dfn-12 ltc3892/ ltc3892-1 60v, low i q , dual 2-phase synchronous step-down dc/dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4.5v v in 60v, 0.8v v out 0.99v in , i q = 29a ltc3891 60v, low i q , synchronous step-down dc/dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a lt ? 8620 65v, 2.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3.4v, v in(max) = 65v, v out(min) = 0.97v, i q = 2.5a, i sd < 1a, msop-16e 3mm 5mm qfn-24 ltc3863 60v, low i q inverting dc/dc controller v in(min) = 3.5v, v in(max) = 60v, v out(min) = ?150v, 3mm 4mm dfn-12, msop-12e lt8611 42v, 2.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a and input/output current limit/monitor v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 2.5a, i sd <1a, 3mm 5mm qfn-24 lt8612 42v, 6a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 3.0a, i sd <1a, 3mm 6mm qfn-28 lt8614 42v, 4a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 2.5a, i sd <1a, 3mm 4mm qfn-18 4.7h l2 c in3 0.1f c in2 22f c vcc2 2.2f c out2 47f 2 c boost2 0.1f c set2 10nf r ith 1.33k c ithp 220pf c ith 3.3nf r t2 100k 3.3h l1 c in1 22f c vcc1 2.2f c out1 47f 2 c boost1 0.1f r set1 240k c set1 10nf r t1 100k r set3 1k r set4 1k r set2 240k run LTC7149 v in gnd boost sw v outsns v out ? s v out ? mode/sync intv cc v inreg ith ?12v 2.5a rail rt 24v run ltc3649 v in imon boost sw v out pgnd v in mode/sync intv cc v inreg iset ith 12v 4a rail rt sgnd iset extv cc extv cc 7149 ta02

▲Up To Search▲

Price & Availability of LTC7149

	To Download LTC7149 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .